The present invention relates to monolithic, semiconductor integrated structures and, more particularly, to an integrated circuit device including a bipolar transistor and an electronic switch which are connected to one another in the xe2x80x9cemitter switchingxe2x80x9d configuration.
As is known, an xe2x80x9cemitter switchingxe2x80x9d configuration includes a vertical bipolar transistor, generally a power transistor for high voltage operation, and an electronic switch in series with the emitter of the bipolar transistor. The electronic switch may be a field effect transistor or a bipolar transistor for low voltage operation connected, by its drain or collector terminal, respectively, to the emitter terminal of the bipolar transistor. The opening of the electronic switch allows an extremely rapid switching off of the high voltage bipolar transistor, so that such a configuration is advantageously used in applications in which the high voltage bipolar transistor is caused to function in rapid switching between its conducting state and its non-conducting state.
A known integrated structure of a device including a vertical bipolar power transistor and a vertical MOS field effect (VDMOS) transistor in the above described configuration is illustrated in FIG. 1. It is formed on a substrate 10 of semiconductor material, for example of N+ monocrystalline silicon, i.e. with a high concentration of N type doping impurities. (It should be noted that in the following description and in the drawings, the concentrations of the N type and P type doping impurities are indicated, as is customary, by adding the sign xe2x88x92 or + to the letters N and P; the letters N and P without the xe2x88x92 or + signs denote concentrations of intermediate values).
Two N type epitaxial layers 11 and 12 with different concentration of doping impurities, indicated by Nxe2x88x92 and N are formed on the substrate 10. The layer 11, together with the substrate 10, contains the collector region of the bipolar transistor. A metallic layer 28 applied to the free surface of the substrate constitutes the collector terminal, which is also one of the terminals of the integrated device.
A Pxe2x88x92 region, indicated by 13, formed between the epitaxial layers 11 and 12, and therefore xe2x80x9cburiedxe2x80x9d between them, constitutes the base region of the bipolar transistor. A base insulation and deep contact P+ region 15 extends from the front surface of the plate, that is to say, from the surface opposed to the metallic layer 28 with the collector terminal C, as far as the edge of the base region 13, delimiting within it an insulated N region, indicated by 16. A second buried N type region 14 having a greater concentration of doping impurities than that of the insulated region 16 is formed on the Pxe2x88x92 region 13 so as to form a junction therewith, and constitutes the emitter region of the bipolar transistor.
Within the insulated region 16 there extends a P region 25, formed by a surface part 25a with low concentration (Pxe2x88x92) and by a deep part 25b with high concentration (P+) of doping impurities, which constitutes the body region of the VDMOS transistor and which contains the channel 17 of the transistor itself.
Within the body region 25 there is formed an N+ region 26 which constitutes the source region of the VDMOS transistor. A strip 22 of electroconductive material, which overhangs the channel and is insulated from the surface of the plate by a thin layer of dielectric, constitutes the gate electrode, which is also a terminal of the device, indicated by G.
Electroconductive surface contact strips 4 and 5 are formed, respectively, on the source region 26 and on the insulation region 15 and constitute, respectively, the source terminal S of the VDMOS transistor, which is also one of the terminals of the integrated device, and the base terminal B of the bipolar transistor. The drain region of the VDMOS transistor includes the part of the insulated N region 16 included between the buried emitter region 14 and the body region 25 and is therefore in common with the emitter region of the bipolar transistor. The region 14, in this example, is not connected to external electrodes. If necessary, however, an N+ deep contact region (sinker) can easily be formed to extend from the front surface of the plate to the N+ region 14 to connect it to an external electrode or to other components integrated in the same plate.
It is intended that the VDMOS structure described above forms, on its own, the electronic switch of the xe2x80x9cemitter switchingxe2x80x9d device, but could also be only a cell of a VDMOS transistor composed of a multiplicity of identical cells.
In order to understand the problem underlying the invention, reference is made to FIG. 2 which shows a diagram of a simple circuit including an emitter switching device of the type described above. The bipolar transistor, of the NPN type, indicated by T1, has the collector C connected to the terminal Vcc of a supply voltage source across a load ZL. The emitter E is connected to the drain D of the VDMOS transistor, indicated by T2, and the base B is connected to both a base polarization terminal Vbb, through a resistor Rb, and to the source S of the VDMOS transistor through a Zener diode DZ. The VDMOS transistor T2 has the source S connected to the second terminal of the supply source, indicated by a ground symbol, and the gate electrode G connected to a terminal of the device to which a command signal Vgs is applied. The polarization voltage Vbb is selected such that the current Ic of the collector is that necessary to feed the load, and the command signal Vgs is selected so as to keep the VDMOS transistor T2 open or closed at pre-established time intervals. The reverse conduction voltage Vz of the Zener diode DZ is selected to have a higher value than the voltage Vbe between base and emitter of the bipolar transistor T1 in conduction.
In operation, the bipolar transistor T1 starts to conduct as soon as the voltage Vgs exceeds the threshold value of the VDMOS transistor T2. During the conduction of the transistor T1, the Zener diode DZ does not conduct because the voltage between the base of T1 and ground is only slightly higher than the voltage Vbe. The higher the efficiency of the bipolar transistor T1 is, and the lower the conduction resistance Ron of the VDMOS transistor T2 is, and the greater the current carrying capacity of the device. In the switched off phase of the device, i.e. when the gate voltage Vgs drops below the threshold voltage of the transistor T2, the transistor T2 cuts off and the emitter current of T1 is canceled out. During this phase, the collector current of T1 flows through the base region of T1 and through the Zener diode DZ to the ground terminal. The lower the resistivity of the base region (13 in FIG. 1), the lower the energy dissipated in this phase.
While the device is switched off, the emitter/drain voltage reaches a value equal to the sum of the voltage BVebo (reverse break voltage of the emitter-base junction of the transistor T1 with collector open) and of the Zener voltage Vz. Therefore the VDMOS transistor T2 must be capable of withstanding this voltage between its drain-source terminals. In other words, the following inequality must be fulfilled:
Bvebo+Vz less than BVdss
where BVdss is the break voltage between drain and source with gate at the source voltage.
In the planning stage, there is a tendency to make the sum of the two terms in the first part of the inequality as small as possible. The voltage Vz is determined by the values of Vbe of the transistor T1 and of Ron of T2 (typically a few volts). The value of BVebo depends on the concentrations of doping impurities in the regions 14 and 13 (FIG. 1). In practice, the concentration of impurities in the base region are increased as much as possible, because, besides reducing the voltage BVebo, it improves the performance of the device in the switched off phase, i.e. when the collector current flows to ground through the base-collector junction and through the Zener diode DZ. However, an increase in the concentration of impurities in the base has two unwanted effects, e.g. a reduction in the gain of the bipolar transistor T1 and an increase in the resistivity of the drain region, since the P type doping of the base region tends to compensate for the doping of the N drain region, thus increasing the resistivity of the drain region. This entails an increase in the resistance in conduction Ron of the VDMOS transistor T2.
An object of the present invention is to provide an integrated circuit device including a bipolar transistor and an electronic switch which are connected to one another in an emitter switching configuration and which will have optimum electrical characteristics, and in particular a high gain of the bipolar transistor and a low resistance of the electronic switch in conduction.
This and other objects, features and advantages in accordance with the present invention are provided by a semiconductor device including a bipolar transistor and an electronic switch which are connected in an emitter switching configuration. The device includes a substrate, an epitaxial layer, having a first type of conductivity, on the substrate and containing at least part of a collector region of the bipolar transistor, and a base region of the bipolar transistor, having a second type of conductivity, and buried in the epitaxial layer. The base region comprises a plurality of zones having different concentrations of doping impurities. Furthermore, the device includes a contact region, having the second type of conductivity, and extending in the epitaxial layer from a front surface of the device to the base region, and a first active region of the electronic switch comprising an insulated region having the first type of conductivity and being delimited by the contact region. Also, the device includes a second active region of the electronic switch, having the second type of conductivity, and extending from the front surface of the device into the insulated region, and a third active region of the electronic switch, having the first type of conductivity, and extending from the front surface of the device into the second active region.
The epitaxial layer may have a relatively lower concentration of doping impurities than the third active region, and the base region may have a relatively lower concentration of doping impurities than the contact region. Further, the device may include a first device terminal contacting the substrate, a second device terminal contacting the base region via the contact region, a third device terminal contacting the third active region, and a fourth device terminal coupled to the second active region. At least some of the plurality of zones, corresponding to portions of the first active region in which there is a more intense flow of charge carriers during device operation, may have a relatively lower concentration of doping impurities than other zones of the plurality of zones. The substrate may have the first type of conductivity or the second type of conductivity.
Also, the insulated region may comprise at least one area having a relatively higher concentration of doping impurities than a remainder of the insulated region, the area having a more intense flow of charge carriers during device operation. The electronic switch may comprise a VDMOS type transistor with a drain region in the first active region, a body region in the second active region, and a source region in the third active region. Alternatively, the electronic switch may comprise a bipolar transistor with a collector region in the first active region, a base region in the second active region, and an emitter region in the third active region. The bipolar transistor may form part of an IGBT type device.